verilogHDL concepts

Introduction

  • Design flow for Digital IC'S
  • what is verilogHDL?
  • features of verilogHDL
  • advantage of verilogHDL
  • History of verilogHDL.
  • why use verilogHDL.
  • verilog HDL Terminology
  • programing vs verilogHDL
  • schematic vs verilogHDL
  • Design approch

  • top down
  • bottom to up
  • Design modelling

  • Data flow
  • Behivioural
  • structural / gate level
  • mixed
  • Verilog Basic modelling structure

  • module
  • ports
  • module identifier
  • module Instance
  • Data Type

  • Net Data type
  • variable
  • Operator

  • non blocking & blocking
  • Airthematic
  • Relational
  • Equality
  • Logical
  • Bitwise
  • Reduction
  • Shift
  • Conditional
  • Concatination
  • Replication
  • Loops

  • for
  • while
  • do while
  • repeat