systemverilog concepts

Introduction

  • What is a Testbench?
  • hat is verification?
  • SystemVerilog Data-types

  • data types
  • Strings
  • user defined data type
  • typedef_datatype
  • Enumeration
  • Structures
  • Union
  • Arrays:

  • Arrays
  • fixed Arrays
  • Dynamic Arrays
  • Associative Arrays
  • Queues
  • SystemVerilog Interface

  • Interfaces
  • Modports
  • Clocking Blocks
  • Program Block
  • SystemVerilog Processes controll

  • fork join
  • fork control
  • Interprocess Communication

  • Interprocess Communication
  • Semaphores
  • Mailboxes
  • SystemVerilog Class

  • Class
  • Class Handles and Objects
  • Constructors
  • this pointer
  • super keyword
  • typedef forward decl.
  • Inheritance
  • Polymorphism
  • Virtual Methods
  • Static Variables/Functions
  • Shallow/Deep Copy
  • Parameterized Classes
  • extern keyword
  • Access Qualifier : local
  • Abstract Class/Pure Methods
  • Randomization
  • Randomization & Constraints

  • Introduction
  • Random variables
  • Constraint blocks
  • Array Randomization
  • Common Constraints
  • inside constraint
  • Implication Constraint
  • foreach Constraint
  • solve before Constraint
  • Static Constraints
  • Practical Constraint Examples
  • Bus Protocol Constraints
  • Randomization Methods
  • In-line constraints
  • Soft constraints
  • Disable constraints
  • Disable randomization
  • Random weighted case
  • SystemVerilog Misc Constructs

  • Dynamic Casting
  • Packages
  • Command-line Input
  • File operations
  • SystemVerilog Functional Coverage

  • Coverage
  • Coverage
  • Functional Coverage
  • Cross Coverage
  • Coverage Options
  • Parameters and `define