modport

Modport is the short farm for module port.Modports are used to specify the direction of signal with respect to a specific module/component and They allow for the definition of different views of the signals within the interface.
In many cases, generaly three modport modports i.e

  • w.r.t DUT
  • w.r.t TB
  • w.r.t monitor
  • or views, are needed.

    Interface Example with modport

    interface.sv

    interface logic_circut_if ();

    logic x1,x2;
    logic [1:0] out;

    // decclaration of modport

    modport dut (input a,b, output out);// signals direction w.r.t Design Under Test (DUT)

    modport tb (output a,b, input out);// signals direction w.r.t Design Testbecnh (TB)

    modport monitor (input a,b, out);// these signals towards Environment so all are inputs

    endinterface

    logic_circut.sv

    module logic_circuit(logic_circut_if.dut intf); //using dot invoke DUT modport name so that signal get direction as per DUT

    assign intf.out = {intf.x2, intf.x1};

    endmodule

    logic_circut_tb.v

    module logic_circuit(logic_circut_if.tb intf); //using dot invoke TB modport name so that signal get direction as per Testbench

    // initial block to used force the stimulus
    initial
    begin
    intf.x2=1'b0; intf.x1=1'b0;
    #10 intf.x2=1'b0; intf.x1=1'b1;
    #10 intf.x2=1'b1; intf.x1=1'b0;
    #10 intf.x2=1'b1; intf.x1=1'b1;
    #10 $stop;
    end

    initial
    $monitor ("intf.x1=%b, intf.x2=%b, intf.out =%b", intf.x1,intf.x2,intf.out, $time );
    endmodule

    logic_circut_tb_top.v

    module logic_circuit_tb_top;

    logic_circut_if intf();
    logic_circuit DUT (intf);
    logic_circuit_tb TB (intf);

    endmodule





    VerilogHDL and systemverilog TB

    interface.sv

    interface logic_circut_if ();

    logic x1,x2;
    logic [1:0] out;

    // decclaration of modport

    modport dut (input a,b, output out);// signals direction w.r.t Design Under Test (DUT)

    modport tb (output a,b, input out);// signals direction w.r.t Design Testbecnh (TB)

    modport monitor (input a,b, out);// these signals towards Environment so all are inputs

    endinterface

    logic_circut.v

    module logic_circuit(x1,x2,out);// in this model modport cant acess bcoz this verilog DUT
    input x1,x2;
    output [1:0] out;

    wire x1,x2;
    wire [1:0] out; // data flow model

    assign out = {x1,x2};

    endmodule

    logic_circut_tb.v

    module logic_circuit(logic_circut_if.tb intf);// invoke tb modport

    // initial block to used force the stimulus
    initial
    begin
    intf.x2=1'b0; intf.x1=1'b0;
    #10 intf.x2=1'b0; intf.x1=1'b1;
    #10 intf.x2=1'b1; intf.x1=1'b0;
    #10 intf.x2=1'b1; intf.x1=1'b1;
    #10 $stop;
    end

    initial
    $monitor ("intf.x1=%b, intf.x2=%b, intf.out =%b", intf.x1,intf.x2,intf.out, $time );
    endmodule

    logic_circut_tb_top.v

    module logic_circuit_tb_top;

    logic_circut_if intf();
    logic_circuit.dut DUT (.x1(intf.x1),(.x2(intf.x2),(.out(intf.out)); // Dot refpresnts dut name connect to interface signal
    logic_circuit_tb.tb TB (intf); // from Top instances we can invoke modports

    endmodule




    VerilogHDL DUT and systemverilog TB with wrapper

    interface.sv

    interface logic_circut_if ();

    logic x1,x2;
    logic [1:0] out;

    // decclaration of modport

    modport dut (input a,b, output out);// signals direction w.r.t Design Under Test (DUT)

    modport tb (output a,b, input out);// signals direction w.r.t Design Testbecnh (TB)

    modport monitor (input a,b, out);// these signals towards Environment so all are inputs

    endinterface

    logic_circut.v

    module logic_circuit(x1,x2,out);
    input x1,x2;
    output [1:0] out;

    wire x1,x2;
    wire [1:0] out; // data flow model

    assign out = {x1,x2};

    endmodule

    logic_circut_dut_wrapper.sv

    module logic_circut_dut_wrapper(logic_circut_if.dut intf); // in dut wrapper instance also invoke modport
    logic_circuit DUT (.x1(intf.x1),(.x2(intf.x2),(.out(intf.out)); // Dot refpresnts dut name connect to interface signal
    endmodule

    logic_circut_tb.sv

    module logic_circuit(logic_circut_if.tb intf);

    // initial block to used force the stimulus
    initial
    begin
    intf.x2=1'b0; intf.x1=1'b0;
    #10 intf.x2=1'b0; intf.x1=1'b1;
    #10 intf.x2=1'b1; intf.x1=1'b0;
    #10 intf.x2=1'b1; intf.x1=1'b1;
    #10 $stop;
    end

    initial
    $monitor ("intf.x1=%b, intf.x2=%b, intf.out =%b", intf.x1,intf.x2,intf.out, $time );
    endmodule

    logic_circut_tb_top.v

    `include "logic_circut.v"
    `include "logic_circut_if.sv"
    `include "logic_circut_dut_wrapper.sv"
    `include "logic_circuit_tb.sv"



    module logic_circuit_tb_top;

    logic_circut_if intf();
    // logic_circuit DUT (.x1(intf.x1),(.x2(intf.x2),(.out(intf.out)); // Dot refpresnts dut name connect to interface signal
    logic_circut_dut_wrapper DUT(logic_circut_if intf); // above commented line not require instead of DUT we can get instance in dut wrapper
    logic_circuit_tb TB (intf);

    endmodule