Interface

SystemVerilog adds a powerful new port type to Verilog, called an interface.
interface is a named bundle or group of signals to provide an abstract encapsulation of communication between blocks.
Which consists of

  • Directional information (modports)
  • Timing (clocking blocks)
  • Functionality (routines,assertions)
  • A simple interface declaration

    interface name_of_interface ();
    -----
    ----- } declaration of signals
    -----
    -----
    ----- } modports
    -----
    -----
    ----- } clocking block
    -----
    -----
    ----- } task, functions and assertions
    -----
    endinterface

    • An interface can be instantiated hierarchically like a module, with or without ports.

    interface Example

    interface name_of_interface ();
    logic a
    logic b
    logic c

    modport DUT (input a,b, output c)
    modport TB (output a,b, input c)
    modport MON (input a,b, input c)

    clocking sd @(posedge ck);
    output #2 a,b ;
    input #3 c;
    endclocking;
    -----
    ----- } task, functions and assertions
    -----
    endinterface

    Connection between testbench and Design

    Design (DUT ) Testbench (TB)
    VerilogHDL/ VHDL VerilogHDL / VHDL
    systemverilog systemverilog
    verilogHDL systemverilog
    verilogHDL systemverilog with wrapper

    Interface Example in Verilog Example

    logic_circut.v

    module logic_circuit(x1,x2,out);
    input x1,x2;
    output [1:0] out;

    wire x1,x2;
    wire [1:0] out; // data flow model

    assign out = {x1,x2};

    endmodule

    logic_circut_tb.v

    module logic_circuit(x1,x2,out);
    input x1,x2;
    output [1:0] out;

    reg x1,x2;
    wire[1:0] out;

    // initial block to used force the stimulus x2=1'b0; x1=1'b0;
    #10 x2=1'b0; x1=1'b1;
    #10 x2=1'b1; x1=1'b0;
    #10 x2=1'b1; x1=1'b1;
    #10 $stop;

    initial
    $monitor ("x1=%b, x2=%b, out =%b", x1,x2,out, $time );
    endmodule

    logic_circut_tb_top.v

    module logic_circuit_tb_top;
    wire x1;
    wire x2;
    wire [1:0]out;

    logic_circuit DUT (x1,x2,out);
    logic_circuit_tb TB (x1,x2,out);
    endmodule


    Disadvantage to connect DUT and TB traditional verilogHDL method:


     Declarations must be duplicated in multiple modules
     Communication protocols must be duplicated in several modules
     Risk of mismatched declarations
     A change in design specifications can require modifications in multiple modules





    systemverilog DUT and systemverilog TB :

    interface.sv

    interface logic_circut_if ();

    logic x1,x2;
    logic [1:0] out;

    endinterface

    logic_circut.sv

    module logic_circuit(logic_circut_if intf);

    assign intf.out = {intf.x2, intf.x1};

    endmodule

    logic_circut_tb.v

    module logic_circuit(logic_circut_if intf);

    // initial block to used force the stimulus
    initial
    begin
    intf.x2=1'b0; intf.x1=1'b0;
    #10 intf.x2=1'b0; intf.x1=1'b1;
    #10 intf.x2=1'b1; intf.x1=1'b0;
    #10 intf.x2=1'b1; intf.x1=1'b1;
    #10 $stop;
    end

    initial
    $monitor ("intf.x1=%b, intf.x2=%b, intf.out =%b", intf.x1,intf.x2,intf.out, $time );
    endmodule

    logic_circut_tb_top.v

    module logic_circuit_tb_top;

    logic_circut_if intf();
    logic_circuit DUT (intf);
    logic_circuit_tb TB (intf);

    endmodule

    Advantages of interface

  • An interface allows a number of signals to be grouped together and represented as a single port
  • The declarations of the signals that make up the interface are contained in a single location.
  • Each module that uses these signals then has a single port of the interface type, instead of many ports with the discrete signals.
  • Design reuse – communication with an oft-used protocol
  • Adding/changing/deleting a signal is easy
  • Enforcing naming conventions, size, direction




  • VerilogHDL and systemverilog TB

    interface.sv

    interface logic_circut_if ();

    logic x1,x2;
    logic [1:0] out;

    endinterface

    logic_circut.v

    module logic_circuit(x1,x2,out);
    input x1,x2;
    output [1:0] out;

    wire x1,x2;
    wire [1:0] out; // data flow model

    assign out = {x1,x2};

    endmodule

    logic_circut_tb.v

    module logic_circuit(logic_circut_if intf);

    // initial block to used force the stimulus
    initial
    begin
    intf.x2=1'b0; intf.x1=1'b0;
    #10 intf.x2=1'b0; intf.x1=1'b1;
    #10 intf.x2=1'b1; intf.x1=1'b0;
    #10 intf.x2=1'b1; intf.x1=1'b1;
    #10 $stop;
    end

    initial
    $monitor ("intf.x1=%b, intf.x2=%b, intf.out =%b", intf.x1,intf.x2,intf.out, $time );
    endmodule

    logic_circut_tb_top.v

    module logic_circuit_tb_top;

    logic_circut_if intf();
    logic_circuit DUT (.x1(intf.x1),(.x2(intf.x2),(.out(intf.out)); // Dot refpresnts dut name connect to interface signal
    logic_circuit_tb TB (intf);

    endmodule




    VerilogHDL DUT and systemverilog TB with wrapper

    interface.sv

    interface logic_circut_if ();

    logic x1,x2;
    logic [1:0] out;

    endinterface

    logic_circut.v

    module logic_circuit(x1,x2,out);
    input x1,x2;
    output [1:0] out;

    wire x1,x2;
    wire [1:0] out; // data flow model

    assign out = {x1,x2};

    endmodule

    logic_circut_dut_wrapper.sv

    module logic_circut_dut_wrapper(logic_circut_if intf);
    logic_circuit DUT (.x1(intf.x1),(.x2(intf.x2),(.out(intf.out)); // Dot refpresnts dut name connect to interface signal
    endmodule

    logic_circut_tb.sv

    module logic_circuit(logic_circut_if intf);

    // initial block to used force the stimulus
    initial
    begin
    intf.x2=1'b0; intf.x1=1'b0;
    #10 intf.x2=1'b0; intf.x1=1'b1;
    #10 intf.x2=1'b1; intf.x1=1'b0;
    #10 intf.x2=1'b1; intf.x1=1'b1;
    #10 $stop;
    end

    initial
    $monitor ("intf.x1=%b, intf.x2=%b, intf.out =%b", intf.x1,intf.x2,intf.out, $time );
    endmodule

    logic_circut_tb_top.v

    `include "logic_circut.v"
    `include "logic_circut_if.sv"
    `include "logic_circut_dut_wrapper.sv"
    `include "logic_circuit_tb.sv"



    module logic_circuit_tb_top;

    logic_circut_if intf();
    // logic_circuit DUT (.x1(intf.x1),(.x2(intf.x2),(.out(intf.out)); // Dot refpresnts dut name connect to interface signal
    logic_circut_dut_wrapper DUT(logic_circut_if intf); // above commented line not require instead of DUT we can get instance in dut wrapper
    logic_circuit_tb TB (intf);

    endmodule