Grouping Statements

In Verilog has two ways of grouping statements
  • begin…end :
  • fork…join :

  • A Verilog fork...join block always causes the process executing the fork statement to block until the termination of all forked processes. With the addition of the join_any and join_none keywords, SystemVerilog provides three choices for specifying when the parent (forking) process resumes execution.

    For Join All :
    The parent process blocks until all the processes spawned by this fork complete.
    Fork Join Any :
    The parent process blocks until any one of the processes spawned by this fork completes.
    Fork Join None:
    The parent process continues to execute concurrently with all the processes spawned by the fork.
    The spawned processes do not start executing until the parent thread executes a blocking statement.

    Example : Fork Join

    module fork_join();
    logic clk,a,b,c;
    initial
    begin
    clk = 0;
    a = 1;
    b = 1;
    #5;
    fork
    begin
    #300 a = 0;
    #200 b = 0;
    #100 c = 1;
    end
    join
    #5
    clk = 1;
    $display ("clk=%b",clk,$time );
    end
    //clk becomes 1 when //time=610
    endmodule

    OUT PUT :

    # ----------------OUTPUT RESULT -----------------------
    # clk=1 610
    # ------------------------------------------------------


    Example : Fork Join_Any

    module fork_join_any();
    logic clk,a,b,c;
    initial
    begin
    clk = 0;
    a = 1;
    b = 1;
    #5;
    fork
    #300 a = 0;
    #200 b = 0;
    #100 c =1;
    join_any
    #5
    clk = 1;
    $display ("clk=%b",clk,$time );
    end
    //clk becomes 1 when //time=110

    endmodule

    OUT PUT :

    # ----------------OUTPUT RESULT -----------------------
    # clk=1 110
    # ------------------------------------------------------


    Example : Fork Join None


    module fork_join_none();
    logic clk,a,b,c;
    initial
    begin
    clk = 0;
    a = 1;
    b = 1;
    #5;
    fork
    #300 a = 0;
    #200 b = 0;
    #100 c =1;

    join_none
    #5
    clk = 1;
    $display ("clk=%b",clk,$time );
    end
    //clk becomes 1 when //time=10

    endmodule

    OUT PUT :

    # ----------------OUTPUT RESULT -----------------------
    # clk=1 10
    # ------------------------------------------------------