Built In Data Types

Overview

Two-state: better performance, reduced memory usage
 Queues, dynamic and associative arrays and automatic storage: reduced memory usage, built in support for searching and sorting
 Unions and packed structures: allows multiple views of the same data
 Classes and structures: support for abstract data structures
 Strings: built in string support
 Enumerated types: code is easier to write and understand

Data Types In Systemverilog

SystemVerilog simplifies the design data intent by distinguishing between data type and data kind.
All data can be specified using two properties, viz., data kind and data type.
Data kind refers to usage as net type or variable type.
Data type refers to possible values a data kind can take.

Integer

There are Two types In Integer data type namely,
  • Two-state Data Types
  • Four State Data Types
  • Two State Data Types

    • Can only have two states 0 or 1 (x and z are mapped to a 0)
    • Used to improve simulation performance and reduce memory usage
    • Keep away from the DUT (since x or z values are converted to a 0 or 1)
    • a 2-state begins simulations with a 0
    • 2-state variables cannot represent an uninitialized state
    • Can legally assign 4-state values to 2-state variables. x and z values are mapped to 0 in two state types
    Data Type Description Example
    bit Unsigned , user defined bit clock, bit [7:0]src_addr
    byte signed , 8 bits byte src_addr
    shortint 16 bits, signed shortint s
    int 32 bits, signed int i
    longint 64, signed shortint s

    4 State Data Types

    • which have Four states 0 , 1, x and z;
    • 4-state begins simulation with x;

    Data Type Description Example
    logic user-defined size logic clock, logic [7:0]src_addr
    wire user desfine size , Unsigned, wire [7:0]src_addr
    reg user-defined size reg [7:0]src_addr
    time 64-bit unsigned time now






    Non Integer Data Types

    Real and Shortreal Type

    The real type is Verilog type. SystemVerilog introduces new shortreal type. It is the same a C float.

    Void Data Type

    The void data type represents nonexistent data. It can be used as the return type of functions to indicate no return value. This type can also be used for members of tagged unions.

    Event Data Type

    The event data type in SystemVerilog extends Verilog named events idea. The event is a handle to a synchronization object. It can be triggered and waited for. It has also persistent triggered state which is maintained during the entire time step. Event variable can be assigned another event variable or null value. It can be passed as argument to tasks. Syntax

    event variable_name [ = initial_value];

    If initial value is not specified then the event variable is initialized to a new synchronization object.
    Example

    event strobe; // new event
    event strobe_1; // strobe_1 is alias to strobe
    event empty = null; // empty event

    Classes

    A Class is a collection of data and a set of subroutines that operate on that data. The data in a class are referred to as class properties, and its subroutines are called methods.A Class is declared using the class...endclass keywords.




    Example 01: Default Values of SV Data Type

    module default_values_of_data_types();

    real pi;
    bit bit_test;
    byte byte_test; // same as above
    logic logic_test;
    reg reg_test;
    wire wire_test;
    int int_test;
    shortint shortint_test;
    longint longint_test;
    integer integer_test;
    time time_test;

    //-------------------- Monitor the Values ---------------------------//
    initial
    begin
    $display("------------ Default Values of SV Data Types-------------");
    $display(" The deafault value of real is = %0f ",pi);
    $display(" The deafault value of bit is = %0b ",bit_test);
    $display(" The deafault value of byte is = %0b ",byte_test);
    $display(" The deafault value of logic is = %0b ",logic_test);
    $display(" The deafault value of reg is = %0b ",reg_test);
    $display(" The deafault value of wire is = %0b ",wire_test);
    $display(" The deafault value of int is = %0d ",int_test);
    $display(" The deafault value of integer is = %0d ",integer_test);
    $display(" The deafault value of time is = %0d ",time_test);
    $display("---------------------------------------------------------");
    end
    endmodule

    OUT PUT :

    # ------------ Default Values of SV Data Types-------------
    # The deafault value of real is = 0.000000
    # The deafault value of bit is = 0
    # The deafault value of byte is = 0
    # The deafault value of logic is = x
    # The deafault value of reg is = x
    # The deafault value of wire is = z
    # The deafault value of int is = 0
    # The deafault value of integer is = x
    # The deafault value of time is = x
    # ---------------------------------------------------------

    Example 02: Default Values of SV Data Type

    module initilize_assign_values();

    real pi;
    bit[7:0] bit_test;
    byte byte_test;
    logic[7:0] logic_test;
    reg[3:0] reg_test;
    wire[3:0] wire_test;
    int int_test;
    shortint shortint_test;
    longint longint_test;
    integer integer_test;
    time time_test;

    //------------- assign the values to data variables -------//
    initial
    begin

    pi=3.1415;
    bit_test=8'b0000_1111;
    byte_test=8'b1100_0011;
    logic_test=8'b1100_1100;
    reg_test=4'b1100;
    int_test= 'd12;
    shortint_test= 'd04;
    longint_test= 'd24;
    integer_test=10.0;
    time_test= 100ns;
    end


    initial
    begin
    $display("---------Initilized Values to data variables -------------");
    $display(" The initilized value to real is = %0f ",pi);
    $display(" The initilized value to bit is = %0b ",bit_test);
    $display(" The initilized value to byte is = %0b ",byte_test);
    $display(" The initilized value to logic is = %0b ",logic_test);
    $display(" The initilized value to reg is = %0b ",reg_test);
    $display(" The initilized value to int is = %0d ",int_test);
    $display(" The initilized value to shortint is = %0d ", shortint_test);
    $display(" The initilized value to longint is = %0d ",longint_test);
    $display(" The initilized value to integer is = %0f ",integer_test);
    $display(" The The initilized value to time is = %0d ",time_test);
    $display("---------------------------------------------------------");
    end
    endmodule

    OUT PUT :

    # ---------Initilized Values to data variables -------------
    # The initilized value to real is = 3.141500
    # The initilized value to bit is = 1111
    # The initilized value to byte is = 11000011
    # The initilized value to logic is = 11001100
    # The initilized value to reg is = 1100
    # The initilized value to int is = 12
    # The initilized value to shortint is = 4
    # The initilized value to longint is = 24
    # The initilized value to integer is = 10.000000
    # The The initilized value to time is = 100
    # ---------------------------------------------------------

    Example 03: bit_logic_operator

    module bit_logic_operator();


    // 2-value
    bit [7:0] a = 8'b10xz_01xz;
    int d = 32'b01xz_01xz_01xz_01xz;


    // 4-value
    logic [7:0] b = 8'b01xz_01xz;
    integer c = 32'b01xz_01xz_01xz_01xz;


    initial
    begin
    $display("------------------------------------------------------");
    $display ("Value of bit a = %0b", a);
    $display ("Value of logic b = %0b", b);
    $display ("Value of integer c = %0b", c);
    $display ("Value of int d = %0b", d);
    $display ("bit + integer = %0b", a + c);
    $display ("logic + int = %0b", b + d);

    a = 10;
    b = 20;
    c = 30;
    d = 40;
    $display ("bit + logic = %0b", a + b);
    $display ("integer + int = %0b", c + d);
    $display("------------------------------------------------------");
    end

    endmodule

    OUT PUT :

    # ------------------------------------------------------
    # Value of bit a = 10000100
    # Value of logic b = 1xz01xz
    # Value of integer c = 1xz01xz01xz01xz
    # Value of int d = 100010001000100
    # bit + integer = x
    # logic + int = x
    # bit + logic = 11110
    # integer + int = 1000110
    # ------------------------------------------------------