Clocking Block

  • Separates the timing and synchronization details from the functionality of your tests.
  • Enables modeling at higher level of abstraction
  • The clocking block provides a means of specifying the timing of synchronous signals relative to their clock.
  • It defines the timing that the testbench will use to sample outputs from the DUT and drive inputs towards the DUT.
  • Drive inputs just after the active edge
  • Sample outputs just before the active edge
  • Features

  • Clock specification
  • Input skew,output skew
  • Cycle delay (##)
  • Declaration of Clocking Block

  • Can be declared as @(posedge clk)
  • An interface can use a clocking block to control timing

  • syntax:

    interface name_of_interface ();

    clocking cb @(posedge clock);
    // Directions are relative to program block
    ---- ;
    ---- ;
    endclocking;

    endinterface